1. Field of the Invention
The invention relates to data slicer circuits and, more particularly, to a method and apparatus for digitizing received demodulated binary frequency shift keyed (FSK) data in a time division duplex wireless telecommunication application, such as a cordless telephone.
2. Discussion of Related Technology
Data slicers are circuits used in many signal processing applications, including many different types of wireless or radio telecommunications. For example, cordless telephones, which include a first and second unit such as a handset and base, may utilize data slicers to interpret analog FSK radio signals passed back and forth between the two units. The two units communicate on a single frequency by allocating alternating time periods for transmission from each unit. Both units include a receiver circuit and a transmitter circuit for receiving and transmitting the FSK signals, respectively, and the data slicer is commonly used in the receiver circuit. In applications such as these, the data slicer serves to receive an analog data signal and convert it to a digital data signal, for use in processors and other digital circuits.
FIG. 1 describes a prior art, non-coherent binary FSK data slicer, designated generally by the reference numeral 10, as used by a receiver circuit 11 of a cordless telephone. The receiver circuit 11 operates to produce a digital baseband data signal RXD from an intermediate radio frequency signal IF. The intermediate frequency signal IF is received into a demodulator 12. The demodulator 12 appropriately demodulates the intermediate frequency IF to produce an analog baseband signal RXA, which is composed of a series of time division duplex (TDD) data frames. The analog baseband data signal RXA is fed into a non-inverting terminal ("+") of a comparator 14 and a threshold detector circuit 16.
The threshold detector circuit 16 produces a slice level VSL that represents a "middle" voltage level of the analog baseband data signal RXA. For the sake of simplicity, all voltage levels are to be measured with respect to a common ground voltage (not shown), unless stated otherwise. The slice level VSL is then fed into an inverting terminal ("-") of the comparator 14. The comparator 14 compares the analog baseband data signal RXA with the slice level VSL in order to drive the digital baseband data signal RXD.
Waveform 20 of FIG. 2 illustrates an ideal analog baseband data signal RXA waveform from the demodulator 12 for two TDD data frames 22 and 24. Each TDD data frame is divided into a transmission interval TX, during which the first unit transmits data to the second unit, and a reception interval RX, during which the first unit receives data from the second unit, each about one msec in duration. In this example, the analog baseband data signal RXA produces a sequence that is "valid", or data-rich, during the reception intervals RX, and is "invalid" or meaningless, during the transmission intervals TX. During the reception interval RX of the TDD data frames, excursions of the waveform below a middle voltage 26 represent a logic "0" bit, and those above the middle voltage represent a logic "1" bit.
One reason that the sequence of data in the baseband data signal RXA is invalid during the transmission intervals TX is that the FSK data slicer 10 is only used in the reception intervals RX. Therefore, since many cordless telephones utilize batteries, the demodulator 12 can be powered down during the transmission interval TX in order to save power. However, this step of powering down creates difficulties in determining the slice level VSL. For example, during the transmission interval TX, the voltage level of the analog baseband data signal RXA can drop and the slice level VSL will be adversely affected. As a result, when a sequence of data begins, such as at the beginning of a reception interval RX, a proper interpretation of the initial logic levels in the sequence is subject to errors due to the incorrect slice level VSL.
Additional difficulties result from the behavior of the intermediate frequency signal IF. As mentioned above, waveform 20 of FIG. 2 demonstrates an "ideal" waveform, wherein the vertical axis is a voltage relating directly to the instantaneous frequency of the intermediate frequency signal IF and the horizontal axis represents time. The ideal waveform 20 would be produced by an ideal receiver circuit in the first unit. However, most conventional cost effective transmitter circuits generate TDD data frames similar to those described in waveform 30. For example, a center voltage of the waveform "droops" in response to high-pass or band-pass characteristics of the receiver circuit processing the voltage waveform, as illustrated by reference arrow 34. In addition, an output center frequency of the waveform is also affected by an overall "balance" of the transmitted sequence. For example, if the sequence has a preponderance of either logic "1s" or logic "0s", the output center frequency from the transmitter in the second unit may be adversely affected by an undesirable response of a low-pass loop filter in a phase-locked loop used by the transmitter. Furthermore, the output center frequency may also change as a result of time-varying loading conditions on the transmitter circuit. For the remaining discussion, these effects will be collectively referred to as pulling. It is understood that the cause and effects of pulling are well known by those of ordinary skill in the art.
Another source of distortion in the TDD data frames is the demodulator 12. The output voltage of the analog baseband data signal RXA is different from one demodulator to the next, due to different factors in manufacturability. In particular, the demodulator 12 has a component commonly referred to as a demodulator quadrature element (not shown). Frequency changes in the analog baseband data signal RXA are influenced by a quality factor of the demodulator quadrature element, and a voltage offset of the analog baseband data signal RXA may be shifted due to demodulator variability. As a result, the demodulator 12 brings a degree of unpredictability to the analog baseband data signal RXA depending from one demodulator to the next. For the remaining discussion, the effects of the variability in the demodulator 12 will be collectively referred to as demodulator distortion. It is understood that the cause and effects of demodulator distortion are well known by those of ordinary skill in the art.
Due to the unique operation of the analog baseband data signal RXA, including the "invalid" data during the transmission interval TX, the effects of pulling, and the effects of demodulator distortion, the generation of the slicing level VSL is difficult for the threshold detector 16. Conventionally, the threshold detector 16 determines the slicing level VSL by calculating the direct current (DC) level, i.e., the long term average of the analog baseband data signal RXA, by simply using a conventional low-pass filter. However, while this solution may seem appropriate for a continuous data stream, a low-pass filter alone is insufficient for TDD data frames. When using TDD data frames, the slicing level VSL will be adversely affected by the voltage level of the analog baseband data signal RXA during the transmission intervals TX. In addition, the pulling and demodulator distortion can offset the analog baseband data signal RXA so that the slice level VSL is incorrect for certain instances of each TDD data frame. Therefore, what is needed is a FSK data slicer that produces a relatively accurate slice voltage level in a TDD environment.
Another difficulty associated with the conventional FSK data slicer 10 in the TDD environment is the operation of the comparator 14. The analog baseband data signal RXA provides each logic level associated with a bit of information over a discrete interval of time before transitioning to the bit. However, the accuracy associated with a bit is relatively low near the bit interval boundaries, i.e., the time periods marking the beginning and the end of a bit interval. As a result, comparisons performed over the entire interval becomes error-prone due to the presence of noise at bit interval boundaries. Alternatively, a comparison that is performed once during a single bit interval is also error-prone because it is not evaluating all of the energy during the entire bit interval. Therefore, what is needed is a FSK data slicer that is tolerant of comparator errors at bit interval boundaries, and that evaluates the symbol energy across the entire bit interval period.
Furthermore, what is needed is a relatively small FSK data slicer that requires only a few pins of a single integrated circuit, is relatively inexpensive to manufacture, and tolerates inconsistencies of manufacturing.